Nios II Processor: The World's Most Versatile Embedded Processor

Altera's Nios® II processor, the world's most versatile processor, according to Gartner Research, is the most widely used soft processor in the FPGA industry. The Nios II processor delivers unprecedented flexibility for your cost-sensitive, real-time, safety-critical (DO-254), ASIC-optimized, and applications processing needs. The Nios II processor supports all Altera® SoC and FPGA families.

What makes the Nios II processor the world's most versatile processor?

Application Nios II
Processor Core
Vendor Description
Altera
Power and cost sensitive Nios II economy core Altera With as low as 600 logic elements, the Nios II economy processor core is ideal for microcontroller applications. The Nios II economy processor core, software tools, and device drivers are offered free of charge.
Real time Nios II standard and fast core Altera

Absolutely deterministic, jitter free real-time performance with unique hardware real-time features

  • Vector Interrupt Controller
  • Tightly Coupled Memory
  • Custom instructions (ability to use FPGA hardware to accelerate a function)
  • Supported by industry-leading real-time operating systems (RTOS)
  • Nios II processor is the ideal real-time processor to use with DSP Builder-based hardware accelerators to provide deterministic, high performance real-time results
Applications processing Nios II fast core Altera With a simple configuration option, the Nios II fast processor core can use a memory management unit (MMU) to run embedded Linux. Both open source and commercially supported versions of Linux for Nios II processors are available.
Altera Embedded Alliance
Safety critical Nios II SC core HCell Certify your design for DO-254 compliance by using the Nios II Safety Critical procesor core along with the DO-254 compliance design services offered by HCell.

Get Started Now

Start your design today with the Nios II processor by purchasing one of the many low-cost evaluation or development kits available for the Nios II processor.

To ship designs featuring the Nios II processor, you will need to purchase a license for the Nios II processor.

Table 1. Processor Selection by System Requirements

Processor
Category
Cost- and Power-Sensitive
Processors
Real-Time
Processors
Applications
Processor
Features ARM®
CortexT®- M1
V1 ColdFire Nios II
Economy
Nios II
Standard
Nios II
Fast
ARM
Cortex-A9 MPCore™
Maximum performance efficiency (MIPS(1) per MHz) - 0.93
0.15
0.64
1.13
2.5
Maximum performance (MIPS(1) at MHz)
Stratix® series
160
at
200
135
at
145
50
at
330
170
at
270
340
at
290
-
Maximum performance (MIPS(1) at MHz)
Arria® SoC
- 84
at
90
45
at
300
115
at
180
270
at
240
4,000
at
800 (2)
Maximum performance (MIPS(1) at MHz) Cyclone® SoC

80
at
100

84
at
90
30
at
175
90
at
145
195
at
175
4,000
at
800 (2)
Maximum performance (MIPS(1) at MHz) HardCopy® series - 246
at
265
45
at
290
180
at
285
345
at
305
-
16-/32-bit instruction set support 16 and 32 16, 32, and 48 32 32 32 32, 16-bit Thumb/Thumb2
Level 1 instruction cache - - - Configurable Configurable 32 KB
Level 1 data cache - - - - Configurable 32 KB
Level 2 cache - - - - - 512 KB
Memory management unit

-

-

-

-

Yes

Yes

Floating-point unit - - - Floating-point custom instruction Floating-point custom instruction Double
precision
Vector interrupt controller Yes - - Yes Yes -
Tightly coupled memory Up to 64K - - Configurable Configurable -
Custom instruction interface - - Up to 256 Up to 256 Up to 256 -
Equivalent logic elements 2,500 6,800 600 1,200 1,800 – 3,200 HPS

Table 2. Processor Performance (MIPS* at fMAX) by Device

Processor Category Cost- and Power-Sensitive Processors Real-Time Processors Applications Processor
Devices ARM
Cortex-M1
V1 ColdFire Nios II
Economy
Nios II
Standard
Nios II
Fast
ARM
Cortex-A9
Cyclone III
(MIPS(1) at MHz)
80 at
145
84 at
90
30 at
215
90 at
145
195 at
175
-
Cyclone III LS
(MIPS(1) at MHz)
- 65 at
70
20 at
150
70 at
110
160 at
140
-
Cyclone IV GX
(MIPS(1) at MHz)
- 70 at
75

30 at
175

70 at
110
190 at
165
-
Arria II GX
(MIPS(1) at MHz)
- 84 at
90
45 at
300
115 at
180
270 at
240
-
Stratix III
(MIPS(1) at MHz)
150 at
230
104 at
112
48 at
340
140 at
230
340 at
290
-
Stratix IV
(MIPS(1) at MHz)
- 135 at
145
50 at
340
155 at
240
340 at
290
-
Stratix V
(MIPS(1) at MHz)
- 135 at
145
50 at
330
170 at
270
320 at
280
-

Notes for Table 1 and Table 2:

  1. Dhrystones 2.1 benchmark
  2. Per processor

Table 3. Processor Selector by Operating System Support

Processor Category Low-Cost Processors Real Time Applications Processor
Features Supplier ARM
Cortex-M1
V1 ColdFire Nios II ARM
Cortex-A9
eCoseCosCentric--Yes-
eCos (Zylin)Zylin--Yes-
embOSSegger-YesYes-
Erika EnterpriceEvidence--Yes-
Euros RTOSEuros--Yes-
LinuxWind River--Yes-
LinuxTimesys--Yes-
LinuxSLS--Yes-
LinuxOpen Source--YesYes
MicroC/OS-IIMicrium--Yes-
oSCANVector--Yes-
ThreadXExpress Logic-YesYes-
uCLinuxOpen Source

--Yes-
VxWorksWind River--No Yes