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This page is organized into categories that align with a Serial Digital Interface II system design flow.
You will find information on how to plan, select, design, implement, and verify your Serial Digital Interface II IP cores for Agilex® 7, Agilex® 5 and Agilex® 3, Stratix® 10 SoC, Arria® 10 SoC, Cyclone® 10 GX SoC, Cyclone® 10 LP SoC, Arria® V SoC, Cyclone® V SoC devices. There are also guidelines on how to bring up your system and debug the Serial Digital Interface II IP design.
Get additional support for Agilex® 7 FPGA Interface Protocol Design, Agilex® 5 FPGA Interface Protocol Design, and Agilex® 3 FPGA Interface Protocol Design step-by-step guided journeys for standard development flows surfacing the key critical resources and documentation.
For other devices, search the Device and Product Support Collections.
1. Device and IP Selection
What features are supported in the SDI II FPGA IP?
Which FPGA Device Family Should I Use?
What is the SDI II FPGA IP Core FPGA Resource Utilization?
2. Design Flow and IP Integration
Documentation
- IP Core User Guide
- Agilex® 7 Devices
- Agilex® 5 Devices
- Stratix® 10 Devices
- Arria® 10 Devices
- Cyclone® 10 GX Devices
- FPGA IP release notes
How do I generate the SDI II FPGA IP core?
How do I generate the SDI II FPGA IP Design Example?
The links below provides step-by-step instruction to generate SDI II FPGA IP Design Example from the Quartus® Prime software:
- Agilex® 7 Devices
- Agilex® 5 Devices
- Stratix® 10 Devices
- Arria® 10 Devices
- Cyclone® 10 GX Devices
How do I compile and test my design?
For Agilex®, Stratix® 10, Arria® 10, and Cyclone® 10 GX devices, the steps to compile and test your SDI II FPGA IP design can be found in the following SDI II FPGA IP Design Example User Guides, under section "Compiling and Testing the Design":
- Agilex® 7 Devices
- Agilex® 5 Devices
- Stratix® 10 Devices
- Arria® 10 Devices
- Cyclone® 10 GX Devices
How can I perform SDI II FPGA IP functional simulation?
For Agilex® F-tile, Stratix®, Arria® 10, and Cyclone® 10 GX devices, below are the steps to generate SDI II FPGA IP functional simulation:
- Enable the simulation option in the SDI II FPGA IP Parameter Editor and generate SDI II FPGA IP Design Example
- Agilex® 7 Devices
- Agilex® 5 Devices
- Stratix® 10 Devices
- Arria® 10 Devices
- Cyclone® 10 GX Devices
3. Board Design and Power Management
Pin Connection Guidelines
- Agilex® 7 Devices
- Agilex® 5 Devices
- Agilex® 3 Devices
- Stratix® 10 Devices
- Arria® 10 Devices
- Cyclone® 10 GX Devices
Schematic Review
- Agilex® 7 Devices
- Agilex® 5 Devices
- Agilex® 3 Devices
- Stratix® 10 Devices
- Arria® 10 Devices
- Cyclone® GX 10 Devices
Power Management
- Agilex® 7 Power Management User Guide
- AN 910: Agilex® 7 Power Distribution Network Design Guidelines
- Agilex® 5 Power Management User Guide
- Agilex® 3 Power Management User Guide
- AN 692: Power Sequencing Considerations for Agilex® 7 Stratix® 10 Arria® 10 and Cyclone® 10 GX Devices
- Early Power Estimator for Stratix® 10 FPGAs User Guide
- Stratix® 10 Power Management User Guide
- Early Power Estimator for Arria® 10 FPGAs User Guide
- AN 711: Power Reduction Features in Arria® 10 Devices
- Early Power Estimator for Cyclone® 10 GX FPGAs User Guide
- Early Power Estimator (EPE) and Power Analyzer
- AN 750: Using the FPGA PDN Tool to Optimize Your Power Delivery Network Design
- Device-Specific Power Deliver Network (PDN) Tool 2.0 User Guide
- AN 721: Creating an FPGA Power Tree
- Quartus® Prime Pro Edition User Guide: Power Analysis and Optimization
- FPGA Power and Thermal Calculator User Guide
Thermal Power Management
- Agilex® 7 Devices
- Agilex® 5 Devices
- Agilex® 3 Devices
- Stratix® 10 Devices
Power Sequencing
- Agilex® 7, Stratix® 10, Arria® 10, and Cyclone® 10 GX Devices
Development Kits
- The following development kits are available for the SDI II IP Core:
- Stratix® 10 GX Signal Integrity Development Kit
- Stratix® V GT Transceiver Signal Integrity Development Kit
- Arria® V GX FPGA development kit
4. Design Examples
- Arria® 10 Device
- Arria® 10 - GX Device Multi-Rate SDI II Pass-Through Using Video & Image Processing Pipeline Reference Design
- Arria® 10 - Multi Rate (Up to 12G-SDI) SDI II with External VCXO Reference Design
- Arria® 10 - Triple Rate SDI II VCXO Removal Reference Design
- AN 746: SDI II Triple-Rate Reference Designs for Arria® 10 Devices
- Arria® 10 - 12G-SDI Audio Reference Design
- Cyclone® 10 GX Device
For additional information, search the following resources: Documentation, Training Courses, Videos, Design Examples, and Knowledge Base.