PCI Express* Reference Designs and Application Notes

from Intel (formerly Altera)

Intel offers a host of PCI Express* (PCIe*) reference designs and application notes. These reference designs and application notes offer ready-made solutions that can leveraged for feasibility studies, device selections, and design proofing on Intel FPGAs and SoCs.

The Intel® FPGA development kits complement the reference designs and application notes by delivering a complete system-level design environment that includes both the hardware and software needed to immediately begin developing designs. Each reference design indicates which Intel FPGA development kit and version of the Quartus® II software were used for its development cycle.

As PCIe is a very configurable IP solution and supports numerous application needs, we cannot offer reference designs for every configuration or application possible. If there is no readily available reference design for your particular configuration or device, you may use a similar design and modify and/or port it as needed to fit your design requirements.

Table 1 describes the various reference designs and application notes available for PCIe applications.

Table 1. Reference Design and Application Note Support

Reference Design Name AN/Wiki/
Other
Dev Kit Used Quartus version Design Flow
Qsys/MW/
Other
EP/RP AVST/
AVMM/
AVMM
with DMA
PCIe Gen &Link Width
PCI Express to External Memory Reference Design AN431 AIIGX FPGA Dev Kit 11.0SP1 Qsys EP AVMM/
AVST
Gen1x4
PCI Express to External Memory Reference Design AN431 SIVGX FPGA Dev Kit 11.0SP1 Qsys EP AVMM/
AVST
Gen2x4
PCI Express High Performance Reference Design AN456 AIIGX FPGA Dev Kit 13.1 Qsys EP AVST Gen1x1,Gen1x4,Gen1x8(HIP),
Gen1x1,Gen1x4(SIP)
PCI Express High Performance Reference Design AN456 AVGT FPGA Dev Kit 13.1 Qsys EP AVST Gen1x1(64),Gen1x4(64),Gen1x8(128),
Gen2x1(64),Genx2x4(128)
PCI Express High Performance Reference Design AN456 CIVGX FPGA Dev Kit 13.1 Qsys EP AVST Gen1x1,Gen1x4(HIP),
Gen1x1(SIP)
PCI Express High Performance Reference Design AN456 CVGT FPGA Dev Kit 13.1 Qsys EP AVST Gen1x1(64),Gen1x4(64),
Gen2x1(64),Gen2x4(128)
PCI Express High Performance Reference Design AN456 SIVGX FPGA Dev Kit 13.1 Qsys EP AVST Gen1x1,Gen1x4(64),Gen1x8(128),
Gen2x1,Gen2x4(64),Gen2x4(128),Gen2x8(128)
PCI Express High Performance Reference Design AN456 SVGX FPGA Dev Kit 13.1 Qsys EP AVST Gen1x1(64),Gen1x4(64),Gen1x8(128),
Gen2x1(64),Gen2x4(128),Gen2x8(128),
Gen3x1(64),Gen3x4(128)
PCI Express Avalon®-MM High-Performance DMA Reference Design AN690 SVGX FPGA Dev Kit 14.0 Qsys EP AVMM with
DMA
Gen3x8
Cyclone® V SoC PCIe Root Port with MSI Rocket-
Boards
CV Soc Dev Kit,
CVGX FPGA Dev Kit
13.1   RP,
EP
  Gen2
PCI SIG* Gen2 x8 Merged Design - Stratix® V Wiki SVGX FPGA Dev Kit 13.1 Qsys EP AVST Gen2x8
PCI SIG Gen3 x8 Merged Design - Stratix V Wiki SVGX FPGA Dev Kit 13.1 Qsys EP AVST Gen3x8
Reference Design: Gen2x4 AVMM DMA - Arria® V Wiki AVGT FPGA Dev Kit 14.0 Qsys EP AVMM with
DMA
Gen2x4
Reference Design: Gen2x4 AVMM DMA - Arria V Wiki AV Starter Kit 14.0 Qsys EP AVMM with
DMA
Gen2x4
Reference Design: Gen2x4 AVMM DMA - Cyclone V Wiki CVGT FPGA Dev Kit 14.0 Qsys EP AVMM with
DMA
Gen2x4
Reference Design - Gen3 x8 Avalon-ST 256-bit - Stratix V Wiki SVGX FPGA Dev Kit 13.1 Other EP AVST Gen3x8
Reference Design - Gen3 x8 AVMM 256-bit DMA - Stratix V (AN690) Wiki SVGX FPGA Dev Kit pre 14.0 Qsys EP AVMM with
DMA
Gen3x8
Reference Design: Gen3 x8 AVMM 256-bit DMA for External DDR3 - Stratix V Wiki SVGX FPGA Dev Kit pre 14.0 Qsys EP AVMM with
DMA
Gen3x8
Stratix V PCIe Gen3x8 AVMM DMA with DDR3 AN708
(in
progress)
SVGX FPGA Dev Kit 14.0 Qsys EP AVMM with
DMA
Gen3x8
Stratix V PCIe with SR-IOV Reference Design ANXXX
(tbd)
SVGX FPGA Dev Kit 14.0   EP    
Arria 10 PCIe with DDR4 Reference Design Wiki (tbd) A10GX FPGA Dev Kit 14.0a10 Qsys EP AVMM with
DMA
Gen3x8

Notes:

  1. EP = Endpoint, RP = Root Port
  2. MW = MegaWizardTM

Figure 1. Typical PCIe Application