Configuration via Protocol

Configuration via Protocol (CvP) is a configuration scheme that allows you to configure the FPGA fabric via the PCI Express® (PCIe®) interface for 14 nm Intel® Stratix® 10 FPGAs, 20 nm Intel Arria® 10 FPGAs, and 28 nm Arria V and Stratix V FPGAs. The autonomous PCIe hard intellectual property (IP) allows the embedded PCIe core to operate before the FPGA is fully configured. This enables the FPGA devices to easily meet the PCIe wake-up time requirement.

Table 1 provides links to the documentation and resources that can help you implement CvP in your system.

Table 1. CvP Documentation and Resources

Resource Description
Documentation
Configuration via Protocol (CvP) Implementation in V-series FPGA Devices User Guide 

This user guide discusses the modes, topologies, features, design considerations, and software for CvP.

Arria 10 CvP Initialization and Partial Reconfiguration over PCI Express User Guide This user guide discusses the modes, topologies, features, design considerations, and software for CvP in 20 nm FPGAs.
FPGA Configuration via Protocol White Paper (PDF) This white paper describes how CvP helps your system meet the PCIe wake-up time requirement in 28 nm FPGAs.
Driver and Tools

Software driver code (14 nm)

(Download the driver code)

This is the code for an open-source Linux* driver to configure the core of an FPGA via CvP. You can use this open-source code as a reference when writing your own driver, or customize this driver to perform CvP operations on your system.

Software driver code (28 nm and 20 nm)

(Download the driver code)

This is the code for an open-source Linux driver to configure the core of an FPGA via CvP. You can use this open-source code as a reference when writing your own driver, or customize this driver to perform CvP operations on your system.