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Agilex™ 7 System Architecture Guided Journey
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Agilex™ 7 System Architecture Guided Journey

The interactive journey helps you navigate the system architecture & planning phase of your design using the Agilex™ 7 FPGA devices.

← Select a different journey
Explore Product Capabilities Discover Altera FPGA and SoC Devices Discover Design Software Discover IP, Platforms, and Solutions Install and Evaluate the Product Install and License Design Software and IP View Release Notes and Notices Browse Trainings, Devkits, and Example Designs Create your System Design Plan Develop your Board Design Plan Estimate your Power and Thermal Consumption Develop your HW/SW Co-design Plan Migrate your Design Develop your Design Plan Develop your Configuration and SEU Mitigation Plan Secure the Intellectual Property of your Design Next Steps Begin Developing your Board Begin Developing your Software Application Begin Developing your FPGA Interface Begin Developing your FPGA Application
info

Please select the desired journey step from the flowchart to view the applicable assets.

info

Please select the desired Explore Product Capabilities sub-step from the flowchart to the left to view the applicable assets:

  • Discover Altera FPGA and SoC Devices
  • Discover Design Software
  • Discover IP, Platforms, and Solutions
info

Please select the desired Install and Evaluate the Product sub-step from the flowchart to the left to view the applicable assets:

  • Install and License Design Software and IP
  • View Release Notes and Notices
  • Browse Trainings, Devkits, and Example Designs
info

Please select the desired Create your System Design Plan sub-step from the flowchart to the left to view the applicable assets:

  • Develop your Board Design Plan
  • Estimate your Power and Thermal Consumption
  • Develop your HW/SW Co-design Plan
  • Migrate your Design
  • Develop your Design Plan
  • Develop your Configuration and SEU Mitigation Plan
  • Secure the Intellectual Property of your Design
info

Please select the desired Next Steps sub-step from the flowchart to the left to view the applicable assets:

  • Begin Developing your Board
  • Begin Developing your Software Application
  • Begin Developing your FPGA Interface
  • Begin Developing your FPGA Application
FPGA Devices
listProduct Summary Tables
listDevice Overview, Datasheets, and Known Issues
listVertical Package Migration Information
Embedded Processors
articleAltera® SoC FPGA HPS Overview
picture_as_pdfNios® V Processor Overview
Clocking and PLL
picture_as_pdfClocking and PLL User Guide: F-Series and I-Series
picture_as_pdfClocking and PLL User Guide: M-Series
Design Software and Tools
picture_as_pdfIntroduction to Quartus® Prime Software
picture_as_pdfThird-party Simulation User Guide: Quartus® Prime Pro Edition
picture_as_pdfProgrammer User Guide: Quartus® Prime Pro Edition
FPGA IP Portfolio
infoAltera® FPGA IP Portfolio
picture_as_pdfIntroduction to Altera® FPGA IP Cores
OFS Framework
infoOpen FPGA Stack (OFS) Overview
Installation
picture_as_pdfAltera® FPGA Software Installation and Licensing Guide
picture_as_pdfQuesta*-Altera® FPGA Edition Simulation User Guide
infoOrder Quartus Prime Software from Digikey
infoOrder Quartus Prime Software from Mouser Electronics
Release Notes and Notices
picture_as_pdfQuartus® Prime Pro Edition Software and Device Support Release Notes
listRelease Notes collection
Customer Advisory Notes
listCustomer Advisory collection
Technical Training
listDevice-specific Technical Training Catalog
Development Kits
infoDevelopment Kits Catalog
listPartner Boards Catalog
infoCables and Adaptors Catalog
Design Examples
listDesign Examples Catalog
Board Design Guidelines
picture_as_pdfBoard Design Guidelines
picture_as_pdfSmartVID and Voltage Regulator Guidelines
picture_as_pdfHigh-Speed Serial Interface Signal Integrity Design Guidelines
IO Interface Planning
articleFast and Easy I/O System Design with Interface Planner
picture_as_pdfUsing the Board-Aware Flow: Quartus® Prime Pro Edition Software
picture_as_pdfGenerating Initial I/O Timing Data and I/O Element Delays for FPGAs
Transceiver Interface Planning
picture_as_pdfUsing Transceiver Interface Planner
Power Estimation
listPower Management Documents Catalog
picture_as_pdfPower and Thermal Calculator User Guide
picture_as_pdfPower Analysis and Optimization User Guide: Quartus® Prime Pro Edition
picture_as_pdfPower and Thermal Analyzer User Guide
Thermal Estimation
listThermal Documents Catalog
OFS Overview
articleOpen FPGA Stack (OFS) Overview
articleOFS Git Repository
Design Migration
picture_as_pdfAltera® FPGA Design Flow for AMD* Xilinx* Users
picture_as_pdfMigrating to Quartus® Prime Pro Edition Software
picture_as_pdfMigrate design from Quartus® Prime Standard Edition to Pro Edition
articleMigrate design from Quartus® Prime Standard Edition to Pro Edition
FPGA Design Guidelines
picture_as_pdfGetting Started User Guide: Quartus® Prime Pro Edition
picture_as_pdfMulti-Project Analysis with Exploration Dashboard
picture_as_pdfDesign Recommendations User Guide: Quartus® Prime Pro Edition
picture_as_pdfHyperflex® Architecture High-Performance Design Handbook
picture_as_pdfF-Series FPGA Development Board: Design Block Reuse Tutorial
articleCreating Reusable Design Blocks: Introduction to IP Reuse with the Quartus® Prime Software training
articleCreating Reusable Design Blocks: IP Design and Implementation with the Quartus® Prime Software training
articleCreating Reusable Design Blocks: IP Integration with the Quartus® Prime Software training
picture_as_pdfF-Series FPGA Development Board: Incremental Block-Based Compilation Tutorial
picture_as_pdfBlock-Based Design User Guide: Quartus® Prime Pro Edition
picture_as_pdfPartial Reconfiguration User Guide: Quartus® Prime Pro Edition 
picture_as_pdfAltera® SoC FPGA Device Design Guidelines
picture_as_pdfBest Practices for Floorplanning Partial Reconfiguration Designs
picture_as_pdfPlatform Designer User Guide: Quartus® Prime Pro Edition
infoAn Essential Reset for Altera® FPGA Devices
picture_as_pdfIncluding the Reset Release IP in Your Design
picture_as_pdfHyperflex® Architecture FPGAs Reset Design Techniques
lockDesign Separation for Functional Safety and Red/Black Separation
Scripting and Automation
picture_as_pdfScripting User Guide: Quartus® Prime Pro Edition
picture_as_pdfSettings File Reference Manual: Quartus® Prime Pro Edition
picture_as_pdfSystem Console Getting Started Tutorial
Overview
picture_as_pdf
articleTraining FPGAs Configuration
Configuration Device
infoAltera® Supported Configuration Devices
picture_as_pdfUsing Generic QSPI Flash on SDM Devices
Generic Flash Programmer
picture_as_pdfGeneric Flash Programmer User Guide: Quartus® Prime Pro Edition
Partial Reconfiguration
picture_as_pdfPartial Reconfiguration User Guide: Quartus® Prime Pro Edition
Configuration via Protocol
picture_as_pdfDevice CvP Implementation User Guide
infoP-tile CvP Example Design for Initialization Mode
infoEnabling and Using the Avalon® Streaming Interface for CvP Update Mode
Update your System Remotely
picture_as_pdfRemote System Update User Guide
articleRemote System Update Using HPS Example Design
Single Event Upset (SEU) Mitigation
picture_as_pdfSEU Mitigation User Guide
Security Methodology
lockSecurity Methodology for Altera FPGA and Structured ASICs User Guide (Sign-in and NDA required)
FPGA Device Security
picture_as_pdfSecurity Overview for SDM-Based FPGA Devices
picture_as_pdfMailbox Client FPGA IP User Guide
picture_as_pdfExecuting SDM Commands via JTAG Interface
lockBlack Key Provisioning Service Quick Start Guide (Sign-in and NDA required)
lockDevice Security User Guide (Sign-in and NDA required)
Security IP
picture_as_pdfSymmetric Cryptographic FPGA Hard IP User Guide
picture_as_pdfSymmetric Cryptographic FPGA Hard IP Release Notes
articleSymmetric Cryptographic Intel® FPGA IP Register Map
Board Development
infoBoard Design Process Hub
Software Development
infoSoftware Development Hub
FPGA Interface Design
infoFPGA Interface Design Hub
FPGA Application Design
infoFPGA Application Design Hub
Related Links
  • Agilex™ 7 FPGA Board Design Guided Journey
  • Agilex™ 7 Software Development Guided Journey
  • Agilex™ 7 FPGA Application Design Guided Journey
  • Agilex™ 7 FPGA Interface Protocol Design Journey
  • Agilex™ 7 FPGA AI Design Guided Journey
  • Agilex™ 7 oneAPI FPGA Guided Journey
  • Agilex™ FPGA Portfolio
  • FPGA Design Resources
  • Altera Premier Support (to request access to secure assets)
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