Intel® Stratix® 10 FPGAs and SoCs deliver breakthrough advantages in performance, power efficiency, density, and system integration: advantages that are unmatched in the industry. Featuring the revolutionary Intel HyperFlex FPGA Architecture and built on the Intel 14 nm Tri-Gate process, Stratix 10 devices deliver 2X core performance gains over previous-generation, high-performance FPGAs with up to 70% lower power.

View Stratix 10 Family Table >>

Stratix 10 FPGA and SoC system integration breakthroughs include:

These unprecendented capabilities make Stratix 10 devices uniquely positioned to address the design challenges in next-generation, high-performance systems in virtually all end markets including wireline and wireless communications, computing, storage, military, broadcast, medical, and test and measurement.

Stratix 10 Videos

View a demo of next generation dual mode transceiver technology in Stratix 10 TX device, capable of 56 Gbps PAM4 and 30 Gbps NRZ modulation.

Take a 3-minute tour from the edge and back on the impact Internet of Things (IoT) is having on data processing and how FPGAs, like Stratix 10 FPGAs, are an invaluable part of meeting future processing needs.

Stratix 10 GX/SX Family Overview Table

Stratix 10 TX Family Overview Table

Stratix 10 MX Family Overview Table

Stratix 10 Family Variants

Variant Description
Stratix 10 GX FPGAs

Stratix 10 GX FPGAs are designed to meet the high-performance demands of high-throughput systems with up to 10 TFLOPS of floating-point performance and transceiver support up to 28.3 Gbps for chip-module, chip-to-chip, and backplane applications.

Stratix 10 SX SoCs

Stratix 10 SX SoCs feature hard processor system with 64 bit quad-core  ARM Cortex-A53 processor available in all densities in addition to all the features of Stratix 10 GX devices.

Stratix 10 TX FPGAs

Stratix 10 TX FPGAs deliver the most advanced transceiver capabilities in the industry by combining H- and E- transceiver tiles. The E-tile provides dual-mode transceiver capabilities, allowing a single transceiver channel to operate up to 56 Gbps in PAM-4 mode or 30 Gbps in NRZ mode. Stratix 10 TX FPGAs also support the other breakthrough innovations of the Stratix GX and SX variants.

Stratix 10 MX FPGAs Stratix 10 MX FPGAs combine the programmability and flexibility of Stratix 10 FPGAs and SoCs with 3D stacked high-bandwidth memory 2 (HBM2) in a single package. Stratix 10 MX FPGAs  support both H- and E- transceiver tiles.

Stratix 10 GX/SX Device Family Table

 

Download PDF Family table
 

Part # Reference

1SG040

1SX040  

1SG065

1SX065

1SG085

1SX085

1SG110

1SX110

1SG165

1SX165  

1SG210

1SX210

1SG250

1SX250

1SG280

1SX280

1SG450

1SX450

1SG550 

1SX550

Stratix 10 Product Line

GX 400

SX 400  

GX 650

SX 650

GX 850

SX 850

GX 1100

SX 1100

GX 1650

SX 1650  

GX 2100

SX 2100

GX 2500

SX 2500

GX 2800

SX 2800

GX 4500

SX 4500  

GX 5500

SX 5500

Equivalent
LEs1
378,000 612,000 841,000 1,092,000 1,624,000 2,005,000 2,422,000 2,753,000 4,463,000 5,510,000

Adaptive Logic

Modules
(ALMs)

128,160 207,360 284,960 370,080 550,540 679,680 821,150 933,120 1,512,820 1,867,680
ALM Registers 512,640 829,440 1,139,840 1,480,320 2,202,160 2,718,720 3,284,600 3,732,480 6,051,280 7,470,720
Hyper-Registers from HyperFlex FPGA Architecture Millions of Hyper-Registers distributed throughout the monolithic FPGA fabric
Programmable Clock Trees Synthesizeable Hundreds of synthesizable clock trees

Maximum
Transceiver
Count

24 48 48 48 96 96 96 96 24 24

GXT Full Duplex

Transceiver Count
(30 Gbps)

16 32 32 32 64 64 64 64 16 16

GX Full Duplex

Transceiver Count
(17.4 Gbps)

8 16 16 16 32 32 32 32 8 8
M20K Memory
Blocks
1,537 2,489 3,477 4,401 5,851 6,501 9,963 11,721 7,033 7,033
M20K Memory
(Mb)
30 49 68 86 114 127 195 229 137 137
MLAB Memory
(Mb)
2 3 4 6 8 11 13 15 23 29

Variable-Precision

DSP Blocks

648 1,152 2,016 2,520 3,145 3,744 5,011 5,760 1,980 1,980
18 x 19
Multipliers
1,296 2,304 4,032 5,040 6,290 7,488 10,022 11,520 3,960 3,960
Fixed Point Performance (TMACS)2 2.6 4.6 8.1 10.1 12.6 15.0 20.0 23.0 7.9 7.9
Single Precision Floating Point (TFLOPS)3 1.0 1.8 3.2 4.0 5.0 6.0 8.0 9.2 3.2 3.2
Maximum User I/O Pins 392 400 736 736 704 704 1,160 1,160 1,640 1,640
PCI Express* 
(PCIe*) Hardened Intellectual
Property (IP)
Block(s) (up to Gen3)
1 2 2 2 4 4 4 4 1 1
Secure Device Manager
 
AES-256/SHA-256 bitsream encryption/authentication, physically unclonable function (PUF), ECDSA 256/384 boot code authentication, side channel attack protection
Hard Processor System4 Quad-core 64 bit ARM Cortex-A53 up to 1.5 GHz with 32 KB I/D cache, NEON* coprocessor, 1 MB L2 cache, direct memory access (DMA), system memory management unit, cache coherency unit, hard memory controllers, USB 2.0 x2, 1G EMAC x3, UART x2, SPI x4, I2C x5, general-purpose timers x7, watchdog timer x4
Notes:

1. LE counts valid in comparing across devices, and are conservative vs. competing FPGAs.
2. Fixed-point performance assumes the use of of pre-adder.
3. Floating-point performance is IEEE 754 compliant single precision.
4. Quad-core ARM Cortex-A53 hard processor system only available in Stratix 10 SX SoCs.

Stratix 10 GX/SX Package Options and I/O Pins

Download PDF Package Table1,2
Part # Reference

1SG040

1SX040

1SG065

1SX065

1SG085

1SX085

1SG110

1SX110

1SG165

1SX165

1SG210

1SX210

1SG250

1SX250

1SG280

1SX280

1SG450

1SX450

1SG550

1SX550

Stratix 10 Product Line

GX 400

SX 400

GX 650

SX 650

GX 850

SX 850

GX 1100

SX 1100

GX 1650

SX 1650

GX 2100

SX 2100

GX 2500

SX 2500

GX 2800

SX 2800

GX 4500

SX 4500

GX 5500

SX 5500

F1152 Pin

35 mm x 35 mm,

1.0 mm pitch

392, 8,

192, 24

392, 8,

192, 24

- - - - - - - -

F1760C Pin

42.5 mm x 42.5 mm,

1.0 mm pitch

-

400, 16,

192, 48

-

-

-

-

-

-

- -

F1760A Pin

42.5 mm x 42.5 mm,

1.0 mm pitch

- -

688, 16,

336, 48

688, 16,

336, 48

688, 16,

336, 48

688, 16,

336, 48

688, 16,

336, 48

688, 16,

336, 48

- -

F2112 Pin

47.5 mm x 47.5 mm,

1.0 mm pitch

- -

736, 16,

360, 48

736, 16,

360, 48

-

-

-

-

- -

F2397 Pin

50 mm x 50 mm,

1.0 mm pitch

- - - -

704, 32,

336, 96

704, 32,

336, 96

704, 32,

336, 96

704, 32,

336, 96

- -

F2597 Pin

55 mm x 55 mm,

1.0 mm pitch 

- - - - - -

1160,8,

576,24

1160,8,

576, 24

1640, 8,

816, 24

1640, 8,

816, 24

Notes:

1. A subset of pins for each package are used for high-voltage, 3.0 V and 2.5 V interfaces.
2. Select devices available with pin migration from Arria® 10 device family to Stratix 10 device family. Contact us for more information.
3. All data is preliminary, and may be subject to change without prior notice.

Download the Stratix 10 Device Family Table (PDF) to view the Stratix 10 FPGA and SoC family package plans with vertical migration support.

Stratix 10 FPGA and SoC Benefits

Achieve Performance Breakthroughts with Industry’s Highest Performance FPGAs and SoCs

Break Through the Bandwidth Barrier

  • Transceiver tiles (L-, H-, and E-tile) with data rates up to 56 Gbps that deliver 7X bandwidth vs. previous generation FPGAs 
    • Dual-mode transceiver (E-tile) supports up to 56 Gbps PAM-4 and 30 Gbps NRZ
    • Up to 144 full duplex transceivers in a single package
  • Over 2.5 Tbps bandwidth for serial memory with support for Hybrid Memory Cube
  • Over 2.3 Tbps bandwidth for parallel memory interfaces with support for DDR4 at 2,666 Mbps

Lower Operating Expense

  • Leveraging Intel's leadership in process technology, Stratix 10 devices offer the most power-efficient technologies
    • Up to 70% lower power than prior-generation high-end FPGAs and SoCs
    • Up to 80 giga floating point operations per second (GFLOPS)/Watt of single-precision floating point power efficiency
  • Quad-core ARM Cortex-A53 processor optimized for performance per watt

Achieve the Highest Level of System Integration

  • Largest monolithic FPGA device with 5.5 million LEs
  • Heterogeneous 3D SiP solutions including transceivers and other advanced components
  • 64 bit quad-core ARM Cortex-A53 to enable hardware virtualization, system management and monitoring capabilities, acceleration pre-processing, and more.

Obtain the most comprehensive high-performance FPGA security capabilities

  • Integrated SDM for flexibility to update configuration code
  • Multi-factor authentication
  • Physically Unclonable Function (PUF)

Get Faster Time to Market

  • Start developing with Arria 10 devices and then migrate to footprint-compatible Stratix 10 devices
  • Complementary Enpirion PowerSoCs offer complete and validated power solution for Stratix 10 FPGAs and SoCs higher performance, lower system power, higher reliability, smaller footprint, and faster time to market to power Stratix 10 FPGAs and SoCs

Achieve high designer productivity with optimized FPGA and SoC design software

  • Quartus Prime Pro Edition optimized for multi-million LE FPGA designs providing
    • Significant reduction in design iterations
    • Hyper-Aware design flow to optimize designs for HyperFlex FPGA Architecture
  • C-based design entry using the Intel FPGA SDK for OpenCL™, offering a design environment that is easy to implement on FPGAs
  • Heterogeneous C-based modeling and hardware design with Intel FPGA SDK for OpenCL
  • Heterogeneous debug, profiling, and whole chip visualization with Intel FPGA SoC EDS featuring ARM Development Studio 5* for Intel SoC FPGAs
Stay Informed

† Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase.  For more complete information about performance and benchmark results, visit www.intel.com/benchmarks.