Stratix® 10 SX SoC FPGA

Stratix 10 SoC FPGA combines a quad-core Arm* Cortex*-A53 MPCore® hard processor system with the groundbreaking Hyperflex™ FPGA Architecture to deliver the performance, power efficiency, density, and integration required for embedded applications.

Stratix 10 SX FPGA Product Table

Benefits

Enabling Designers to Do More with HPS While Balancing Power Efficiency

With an embedded hard processor system (HPS) based on a quad-core Arm® Cortex®-A53 MPCore® processor, Stratix 10 SoC FPGAs deliver power-efficient, application-grade performance and enable designers to implement hardware-assisted virtualization directly in the FPGA fabric.

Achieve High Levels of System Integration

Stratix 10 SoC FPGA empowers the USR in the ARM* ecosystem. ARM's next-generation 64-bit architecture (ARMv8) enables hardware virtualization, system management and monitoring capabilities, and acceleration pre-processing. The ARM* Cortex-A53* processor supports 32-bit execution mode and board support packages for popular operating systems, including Linux*, Wind River’s VxWorks*, Micrium’s uC/OS-II* and uC/OS-III*, and more.

Achieve High Designer Productivity with Optimized FPGA and SoC FPGA Software

Optimized for multi-million logic elements (LE), the Virtual Platform streamlines design iterations, fostering early software development. C-based design with FPGA SDK for OpenCL™ offers an easy-to-implement environment on SoC FPGA. The SoC FPGA Embedded Development Suite (EDS) enables debugging, profiling, and whole-chip visualization with the ARM* Development Studio 5* (DS-5*) FPGA Edition Toolkit.

Key Features

Hard Processor System (HPS)

At the heart of the HPS is a highly efficient quad-core ARM* Cortex*-A53 processor cluster, and this processor is optimized for ultra-high performance per watt, which reduces power consumption. The HPS includes a System Memory Management Unit, Cache Coherency Unit, a hard memory controller, and a rich feature set of embedded peripherals.

Digital Signal Processing (DSP)

With Stratix 10 devices, DSP designs can achieve up to 8.6 Tera floating point operations per second (TFLOPS) of IEEE 754 single-precision floating-point operations.

Secure Device Manager (SDM)

SDM controls key operations, such as configuration, device security, single event upset (SEU) responses, and power management. It creates a unified, secure management system for the entire device, including the FPGA fabric, hard processor system (HPS) in SoCs, embedded hard IP blocks, and I/O blocks.