The Intel® Stratix® 10 Support page contains information to help you get started with Stratix 10 designs, including videos, documentation, and training courses.

Training

Free Intel HyperFlex FPGA Architecture Online Training

Course Title

Description

Stratix 10 HyperFlex FPGA Architecture Overview Learn about the new HyperFlex FPGA Architecture, featured in Stratix 10 devices, that enables your designs to achieve 2X performance compared to previous-generation devices.
Quartus Prime Hyper-Aware Design Flow Learn the new features of the Quartus Prime software flow that help you to take advantage of the new Stratix 10 HyperFlex FPGA Architecture.
Using Fast Forward Compile Learn how to use the new Quartus Prime software Fast Forward Compile feature to perform rapid design performance exploration to achieve your target performance goals.
Introduction to Hyper-Retiming Learn how Hyper-Retiming works with the HyperFlex FPGA Architecture and how it is different from conventional FPGA retiming strategies.
Eliminating Barriers to Hyper-Retiming Learn what design situations and coding styles prevent you from achieving the maximum performance gains with Hyper-Retiming in the Stratix 10 HyperFlex FPGA Architecture.
Introduction to Hyper-Pipelining Learn how Hyper-Pipelining works with the HyperFlex FPGA Architecture and how it is different from conventional FPGA pipelining strategies.
Understanding Critical Chains Learn to analyze critical chains and how to solve them to achieve higher clock speeds.
Introduction to Hyper-Optimization Learn how Hyper-Optimization works and how to determine if it is required to achieve your target design goals.
Hyper-Optimization Techniques 1: Loop Analysis and Solutions Learn about the typical types of performance bottlenecks caused by loops in FPGA designs and basic strategies to prevent loops from limiting design performance in Stratix 10 devices.
Hyper-Optimization Techniques 2: Pre-Computation Learn the methods and techniques behind pre-computation to reduce the impact of loops on design performance in Stratix 10 devices.
Hyper-Optimization Techniques 3: Shannon’s Decomposition Learn how the special optimization technique, Shannon’s Decomposition, can be used to minimize the impact of loops for designs targeting Stratix 10 devices.

HyperFlex FPGA Architecture Instructor-Led/Virtual Training

Course Title Description
Performance Optimization with Stratix 10 HyperFlex FPGA Architecture In the Performance Optimization with Stratix 10 HyperFlex FPGA Architecture course, you will learn Quartus Prime software features and some basic design techniques that will enable your designs to take advantage of the Stratix 10 HyperFlex FPGA Architecture. In the training, you will learn two steps to improving your performance with the HyperFlex FPGA Architecture, with each step allowing you to move you up the performance curve.
Advanced Optimization with Stratix 10 HyperFlex FPGA Architecture In the Advanced Optimzation with Stratix 10 HyperFlex FPGA Architecture course, you will learn design techniques that will enable you to unleash the full potential of the Stratix 10 HyperFlex FPGA Architecture. In the training, you will learn how to modify your coding style and logic structures and, as a result, allow your design to achieve clock rates of up to two times when compared to a non-optimized design, without changing overall design functionality.

Quartus® Prime Pro Edition for Stratix 10 Available

Stratix 10 FPGA design software includes compilation support for Intel HyperFlex® FPGA Architecture, High Speed Serial Interface Protocol intellectual property (IP), External Memory Interface IP, and other Intel FPGA IP optimized for Stratix 10.  In addition the full suite of Quartus® Prime Pro Edition productivity tools are available to help you develop your complete Stratix 10 design.  Contact your sales representative for licensing information and to obtain access today.