Intel® FPGA IP for External Memory Interfaces - Support Center

Welcome to the External Memory Interface (EMIF) support page! Here you will find information regarding Intel® Stratix® 10, Arria® 10, and Cyclone® 10 FPGAs on how to plan, design, implement, and verify your external memory interfaces. You will also find debug, training and other resource materials on this page.

This page is set up to walk you through the design process from start to finish.

For support resources regarding other FPGA devices, search within the following links: Documentation Archive, Training Courses, Videos and Webcasts, Design Examples, and Knowledge Base.

What's New

 Intel® Stratix® 10Arria® 10, and Cylcone® 10 EMIF IP User Guides (formerly EMIF Handbook Volumes 1 to 3)

 Intel® Stratix® 10, Arria® 10, and Cylcone® 10 EMIF IP Design Example User Guides

 Intel® Stratix® 10 MX HBM2 IP User Guide 

 EMIF Device Selector now supports Stratix 10 MX Devices containing High Bandwidth Memory (HBM2) 

Two tools are available to help you select an Intel® FPGA device based on your memory requirements: 

  EMIF Device Selector EMIF Spec Estimator
Features
  • Determines memory interfaces needed to achieve a desired bandwidth
  • Calculates bandwidth based on selected memory configurations
  • Displays all Intel® Stratix® 10 and Intel® Arria® 10 FPGAs supporting selected memory interfaces
  • Determines required Intel® FPGA device family and speed grade needed to achieve desired performance
  • Displays maximum frequency and DQ width available based on memory selections

Device Support
  • Intel® Stratix® 10 FPGAs
  • Intel® Arria® 10 FPGAs
  • All Intel® FPGAs
Resources

To learn about the various memory Intellectual Property (IP) available, refer to the following online training curriculum:

Training Course  Description 

Introduction to Memory Interfaces IP in Intel® Stratix® 10 and Arria® 10 Devices

This course covers the different external memory interface options available, as well as the architectural and hard memory controller features for Intel Stratix® 10 and Arria® 10 FPGAs

Introduction and Architecture Overview for High Bandwidth Memory (HBM2) Interfaces in Intel® Stratix® 10 MX Devices

This course covers the benefits of integrating High Bandwidth Memory into the Stratix® 10 MX FPGA devices, features and options for the hardened HBM controller, and how to generate the HBM2 IP

Controller Features for High Bandwidth Memory (HBM2) Interfaces in Intel® Stratix® 10 MX Devices

This course covers the features and options for the hardened HBM controller, and the Arm AMBA 4 AXI interface between the controller and user logic

SoC Hardware Overview  This course covers the features of the Hard Processor Subsystem (HPS) SDRAM and the AMBA AXI bridge architecture 
Introduction to Hybrid Memory Cubes  This course covers the features of Hybrid Memory Cube (HMC) and its architecture 

For information regarding the External Memory Interface (EMIF) Intellectual Property (IP), refer to the following External Memory Interfaces IP User Guides:

For detailed information regarding External Memory Interface (EMIF) Intellectual Property (IP) parameters, refer to the following protocol-specific sections within the following EMIF IP User Guides: 

  Intel® Stratix® 10 Intel® Arria® 10 Intel® Cyclone® 10
EMIF IP Parameter Descriptions
For step-by-step instructions on how to generate the EMIF IP and how to create a reference design example, refer to the appropriate External Memory Interfaces IP Design Example User Guide and videos:

Note: The video is applicable to Intel® Stratix® 10 devices as well.

For step-by-step instructions on how to integrate multiple EMIF IP cores into a single Platform Designer (formerly Qsys) system, refer to the following guide and video:

Note: The design guide is applicable to Intel® Stratix® 10 devices as well.

For information on how to implement the various memory IP available, refer to the following online training curriculum:

Training Course  Description 

Implementing High Bandwidth Memory (HBM2) Interfaces in Intel® Stratix® 10 MX Devices

This course covers how to generate and implement a FPGA design that can access HBM2

Implementing the Hybrid Memory Cube Controller IP in Intel® Arria® 10 Devices

This course covers how to generate and implement a FPGA design that can access the Hybrid Memory Cube device

For detailed information on simulating the External Memory Interface (EMIF) Intellectual Property (IP), refer to the following section within the EMIF IP User Guides:

For instructions on how to generate an EMIF simulation design example and how to run simulations using the ModelSim*-Intel® FPGA simulation software, refer to the following sections within the EMIF IP Design Example User Guides:

For information on how to verify an EMIF design, refer to the following online training curriculum:

Training Course  Description 

Verifying Memory Interfaces IP in Arria® 10 Devices

This course covers how to verify functional of an EMIF design through simulation and how to perform timing analysis

For detailed External Memory Interface (EMIF) pin information, refer to the following protocol-specific sections within the following EMIF Intellectual Property (IP) User Guides: 

  Intel® Stratix® 10 Intel® Arria® 10 Intel® Cyclone® 10
EMIF Pin and Resource Planning

For simplified I/O placement refer to the Interface Planner for an easy-to-use drag-and-drop tool available in the Intel® Quartus® Prime Pro Edition software for Intel® Arria® 10 and Intel® Stratix® 10 FPGAs. Refer to the following videos for information on how to use the Interface Planner and its benefits:

For more information on Interface Planner for resource location assignments, refer to the following online training curriculum:

Training Course  Description 

Fast & Easy I/O System Design with Interface Planner

This course covers how to implement a design resource floorplan using Interface Planner

What is Ping Pong PHY?

Ping Pong PHY allows two memory interfaces to share Address and Command buses. This is supported for DDR3 and DDR4 protocols and for Stratix® V, Intel® Arria® 10, and Intel® Stratix® 10 FPGAs. Refer to the following video for information on the concept of Ping Pong PHY, its benefits, and an analysis of simulation results:

How Do I Generate the HPS EMIF IP?

For a quick reference guide on Hard Processor Subsystem (HPS) External Memory Interface (EMIF) limitations, Intellectual Property (IP) generation, and pin constraints, refer to the following guidelines:

Where Do I Find Information on PHYLite?

The PHYLite IP allows you to build custom memory interface PHY blocks for Intel® Arria® 10 and Intel® Stratix® 10 FPGAs. For detailed information about the PHYLite IP, refer to the following user guide:

For detailed information on how to properly assign pinouts for PHYLite based on different DQ/DQS group sizes, refer to the following video:

Note: The video is applicable to Intel® Stratix® 10 devices as well.

The PHYLite IP supports many different I/O standards and termination values on input and output buffers for Intel® Arria® 10 and Intel® Stratix® 10 FPGAs. Refer to the following video for infroamtion on how to create an On-Chip-Termination (OCT) block and how to associate it with the terminated I/O buffer in the PHYLite IP:

For detailed External Memory Interface (EMIF) board layout and design information, refer to the following protocol-specific sections within the following EMIF Intellectual Property (IP) User Guides: 

  Intel® Stratix® 10 Intel® Arria® 10 Intel® Cyclone® 10
EMIF Board Design Guidelines

For information on measuring write-and-read Intersymbol Interference (ISI) and Crosstalk, arranging Command, Address, Control and Data pins, and I/O bank placement restrictions, refer to the following guidelines:

Note: The Intel® Arria® 10 channel guidelines is applicable to Intel® Stratix® 10 devices as well.

Two tools are available to help you calculate board skew and channel loss: 

  Board Skew Parameter Tool Channel Loss Calculation Tool
Features
  • Calculates board skew due to PCB traces and multi-rank designs
  • Calculates channel loss due to Intersymbol Interference (ISI) and Crosstalk on Command, Address, Control, and Data signals
Support
  • All Intel® FPGAs
  • All memory protocols
  • Intel® Arria® 10 and Intel® Stratix® 10 FPGAs
  • DDR memory protocols
  • Compatible with Mentor Graphics HyperLynx Signal Integrity software only
Resources

For information regarding External Memory Interface (EMIF) timing closure, refer to the following section within the EMIF Intellectual Property (IP) User Guides:

For information regarding debugging the External Memory Interface (EMIF) Intellectual Property (IP), refer to the following section within the EMIF IP User Guides:

The main tool available for debug is the EMIF Debug Toolkit: 

  EMIF Debug Toolkit
Features
  • Displays pre and post calibration margins per DQS group and DQ pin
  • Generates read/write eye diagrams per DQ pin (2-D eye diagram)
  • Allows customizable real-time traffic generator for test/debug (Traffic Generator 2.0)
  • Captures read/write margins during user-mode traffic (Driver Margining)
Support
  • Compatible with EMIF design example projects and custom EMIF designs containing one or more memory interfaces
  • Supports all memory protocols
Accessibility
  • Accessible through the Intel® Quartus® Prime software (Tools > System Debugging Tools > External Memory Interface Toolkit)

How Do I Use the EMIF Debug Toolkit?

For step-by-step instructions on how to daisy-chain multiple memory interfaces for compatibility with the EMIF Debug Toolkit, refer to the following user guide:

The Read/Write 2-D Eye Diagram feature available in the EMIF Debug Toolkit generates read-and-write eye diagrams for each data pin. Refer to the following video for information on important voltage reference parameters during the EMIF IP generation process and how to use the 2-D Eye Diagram feature:

The Traffic Generator 2.0 allows you to test and debug your external memory interface through customizable traffic and test patterns. Refer to the following guide and videos for detailed information on how to use the Traffic Generator 2.0 feature:

The Driver Margining feature allows you to capture read-and-write margining data per pin during user-mode traffic. Refer to the following videos for information on the differences between driver margining and calibration margining, and instructions on how to use the Driver Margining feature:

For information on how to debug an EMIF design, refer to the following online training curriculum:

Training Course  Description 

On-Chip Debugging of Memory Interfaces IP in Arria® 10 Devices

This course covers how to perform debug using the EMIF Toolkit or On-Chip Debug Toolkit, how to use Traffic Generator 2.0, and configure multiple memeory interface designs for compatibility with these debug tools

For information on supported features for the External Memory Interface (EMIF) Intellectual Property (IP), refer to the following release notes:

For information on current and known issues regarding the EMIF IP, refer to the Knowledge Base:

Other Technologies