External power supplies provide the electrical energy needed for proper operation both internally and externally to an FPGA or CPLD. When implementing power supply solutions, designers need to understand the total power required from these supplies (also referred to as “rail power”). Furthermore, designers need to consider how much of that total power is actually dissipated within the device (referred to as “thermal power” or “dissipated power”) as compared to the portion of total power that is dissipated outside the device, such as in external output capacitive loads and balanced resistor termination networks.

The total power consumed by a device, output loading, and external termination networks (if present) is generally comprised of the following major power components:

• Standby
• Dynamic
• I/O

Standby power is from I_CCINT current in the device in standby mode. Core dynamic power is from internal switching within the device (charging and discharging capacitance on internal nodes). I/O power is from external switching (charging and discharging external load capacitance connected to device pins), I/O drivers, and external termination network (if present).

The thermal power is the component of total power that is actually dissipated within the device package, with the remainder being dissipated externally. The actual thermal power dissipated within the device is what designers should consider when deciding if the device’s intrinsic heat transfer ability (referred to as thermal resistance) is sufficient to keep internal die-junction temperatures within normal operating specifications, or if additional thermal solutions, such as aluminum heat sinks, are required for even better heat transfer performance. In general, standby power, dynamic power, and a portion of I/O power will comprise the actual thermal power component of total power.

Standby Power

The device consumes power during standby due to leakage currents. The amount varies with die size, temperature, and process variations. Standby power can be simulated before full device characterization and can be defined in two categories: typical and maximum power.

Stratix® II devices use a 90 nm process technology optimized for power and performance. Compared to previous process technology devices, 90 nm devices dissipate more power due to leakage, becoming a significant component of overall power. Standby power exhibits a strong dependence on die-junction temperature at the 90 nm process node, more so than previous process technologies. Designers need to focus on keeping junction temperature to a minimum to lower the standby component of total power. Figure 1 shows the relationship between standby power and junction temperature.

Dynamic Power

Internal nodes changing logic levels consume dynamic power internal to the device, as power is needed to charge and discharge internal capacitances in the logic array and interconnect networks (e.g., from a logic 0 to logic 1). Core dynamic power includes both routing power and logic element (LE) power (or adaptive logic module (ALM) in the case of Stratix II). LE/ALM power is consumed from charging and discharging internal node capacitance, as well as from internal resistive elements. Routing power is from current required to charge and discharge the external routing capacitance driven by each LE/ALM. Core Dynamic power can also include architectural resources such as:

• RAM blocks (M512, M4K, and M-RAM)
• DSP-multiplier blocks
• Phase locked loops (PLLs)
• Clock tree networks
• High-speed differential interface (HSDI) transceivers

The total dynamic power is calculated by multiplying the VCCINT (1.2V for Stratix II) by the total sum of currents from each architectural feature listed above:

Dynamic power = V_CCINT × Σ I_CCINT (LE/ALM, RAM, DSP, PLL, Clocks, HSDI, Routing)

Equivalent (lumped) capacitance values are used to calculate dynamic power, and are based on the sum of multiple capacitances. For example, pin, trace, and package capacitances are summed for a signal driving an input or output. This approximation is sufficient if internal switching frequencies are accurately determined. Intel utilizes approximation curves (based on characterization data) to determine internal switching frequencies, effectively estimating dynamic power for most design topologies. Estimating the total power consumed by all of a device’s resources takes into account the maximum switching frequency of the resource, estimated toggle-factors, fan-outs to downstream logic, and coefficients for each resource obtained through device characterization. These components are implemented in all aspects of Intel’s PowerPlay suite of power analysis and optimization tools for power estimation and analysis.

I/O Power

I/O power is V_CCIO power, consumed due to the charging and discharging of external load capacitors connected to the device output pins, the output driver circuits operating in resistive modes, and any external termination networks (if present). Device I/O power is computed as:

I/O power = (number of active output drivers × power dissipation coefficient) + 0.5 × (Sum of die-pad, package trace, pin, and output load cap) × I/O standard voltage-swing × f_MAX × (toggle-factor/100) × V_CCIO

The number of active output drivers includes active bidirectional outputs. In addition to the I/O power computed above, there are other contributing components to I/O power, including elements of the I/O buffer which are also powered by V_CCIO. Figure 2 shows a model of the I/O buffer.

As mentioned earlier, a portion of V_CCIO power will be actually dissipated within the FPGA or CPLD, as compared to being dissipated externally via termination resistor networks and/or output capacitive loads. Designers need to consider the internal dissipated power from V_CCIO when planning thermal management solutions (either intrinsic to the device or via external heat sinks). Designers should consider external dissipation components as part of the total requirement for power delivery from the V_CCIO voltage regulators or converters (referred to as rail power). Intel's power analysis technology reports thermal power versus total/rail power starting with Stratix II devices. Future devices will also have this power analysis technology reporting capability.

Other Power Considerations

There are several other factors designers should consider in regards to total power when designing with FPGAs and CPLDs: inrush current, configuration power, and V_CCPD (Stratix II devices only).

Inrush Current

Inrush current is what the device requires during initial power-up stage. During the power-up stage, a minimum level of logic array current (I_CCINT) must be provided to the device, for a specific duration of time. This duration depends on the amount of current available from the power supply. If more current is available, V_CCINT can ramp up faster. When the voltage reaches as high as 90 percent of its nominal value, the initial high current is usually no longer required. The maximum inrush current varies inversely with the temperature of the device. As device temperature increases, the inrush current required during power-up decreases (although the standby current will increase, given its function of temperature).

Configuration Power

In the case of a conventional FPGA, configuration power is the power required to configure the device. During configuration and initialization, the device requires power to reset registers, enable I/O pins, and enter operating mode. The I/O pins are tri-stated during the power-up stage, both before and during configuration, to reduce power and to prevent them from driving out during this time. Refer to the configuring Stratix II devices (PDF) chapter in Volume 2 of the Stratix II device handbook for more information about configuration schemes in Stratix II devices, as well as the applicable configuration pins the V_CCPD for the voltage.

V_CCPD

V_CCPD is a separate, smaller load-current power supply for output predriver circuitry, as well as configuration and Joint Test Action Group (JTAG) I/O buffers. V_CCPD should be connected to 3.3 V in order to power the 3.3 V / 2.5 V buffers that drive configuration input and JTAG pins. Refer to the DC & Switching characteristics (PDF) chapter in the Stratix II device handbook for the V_CCPD specification.